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512MB Unbuffered SODIMM(based on sTSOP)
DDR SDRAM
DDR SDRAM Unbuffered SODIMM
200pin Unbuffered SODIMM based on 256Mb E-die (x8) with 64-bit Non ECC
Revision 1.3 March. 2004
Rev. 1.3 March. 2004
512MB Unbuffered SODIMM(based on sTSOP)
Revision History
Revision 1.0 (May, 2003) - First release Revision 1.1 (August, 2003) - Corrected typo. Revision 1.2 (December, 2003) - Corrected typo. Revision 1.3 (March, 2004) - Corrected package dimension.
DDR SDRAM
Rev. 1.3 March. 2004
512MB Unbuffered SODIMM(based on sTSOP)
200Pin Unbuffered SODIMM based on 256Mb E-die (x8)
Ordering Information
Part Number M470L6423EN0-C(L)B3/A2/B0 Density 512MB Organization 64M x 64
DDR SDRAM
Component Composition 32Mx8 (K4H560838E) * 16EA
Height 1,250mil
Operating Frequencies
B3(DDR333@CL=2.5) Speed @CL2 Speed @CL2.5 CL-tRCD-tRP 133MHz 166MHz 2.5-3-3 A2(DDR266@CL=2) 133MHz 133MHz 2-3-3 B0(DDR266@CL=2.5) 100MHz 133MHz 2.5-3-3
Feature
* Power supply : Vdd: 2.5V 0.2V, Vddq: 2.5V 0.2V * Double-data-rate architecture; two data transfers per clock cycle * Bidirectional data strobe(DQS) * Differential clock inputs(CK and CK) * DLL aligns DQ and DQS transition with CK transition * Programmable Read latency 2, 2.5 (clock) * Programmable Burst length (2, 4, 8) * Programmable Burst type (sequential & interleave) * Edge aligned data output, center aligned data input * Auto & Self refresh, 7.8us refresh interval(8K/64ms refresh) * Serial presence detect with EEPROM * PCB : Height 1,250 (mil), double (512MB) sided * SSTL_2 Interface
* 54pin sTSOP(II)-300 package
SAMSUNG ELECTRONICS CO., Ltd. reserves the right to change products and specifications without notice.
Rev. 1.3 March. 2004
512MB Unbuffered SODIMM(based on sTSOP)
Pin Configurations (Front side/back side)
Pin 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 Front VREF VSS DQ0 DQ1 VDD DQS0 DQ2 VSS DQ3 DQ8 VDD DQ9 DQS1 VSS DQ10 DQ11 VDD CK0 /CK0 VSS Pin 67 69 *71 *73 75 *77 *79 81 *83 85 87 *89 *91 93 *95 97 99 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 Front DQ27 VDD CB0 CB1 VSS DQS8 CB2 VDD CB3 DU VSS CK2 /CK2 VDD CKE1 DU A12 A9 VSS A7 A5 A3 A1 VDD A10/AP BA0 /WE /CS0 *DU(A13) VSS DQ32 DQ33 VDD DQS4 Pin 135 137 139 141 143 145 147 149 151 153 155 157 159 161 163 165 167 169 171 173 175 177 179 181 183 185 187 189 191 193 195 197 199 Front DQ34 VSS DQ35 DQ40 VDD DQ41 DQS5 VSS DQ42 DQ43 VDD VDD VSS VSS DQ48 DQ49 VDD DQS6 DQ50 VSS DQ51 DQ56 VDD DQ57 DQS7 VSS DQ58 DQ59 VDD SDA SCL VDDSPD VDDID Pin 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 Back VREF VSS DQ4 DQ5 VDD DM0 DQ6 VSS DQ7 DQ12 VDD DQ13 DM1 VSS DQ14 DQ15 VDD VDD VSS VSS Pin 68 70 *72 *74 76 *78 *80 82 *84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 *122 124 126 128 130 132 134 Back
DDR SDRAM
Pin 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 Back DQ38 VSS DQ39 DQ44 VDD DQ45 DM5 VSS DQ46 DQ47 VDD /CK1 CK1 VSS DQ52 DQ53 VDD DM6 DQ54 VSS DQ55 DQ60 VDD DQ61 DM7 VSS DQ62 DQ63 VDD SA0 SA1 SA2 DU
KEY
DQ16 DQ17 VDD DQS2 DQ18 VSS DQ19 DQ24 VDD DQ25 DQS3 VSS DQ26
KEY
DQ20 DQ21 VDD DM2 DQ22 VSS DQ23 DQ28 VDD DQ29 DM3 VSS DQ30
DQ31 VDD CB4 CB5 VSS DM8 CB6 VDD CB7 *DU/(RESET) VSS VSS VDD VDD CKE0 DU(BA2) A11 A8 VSS A6 A4 A2 A0 VDD BA1 /RAS /CAS /CS1 DU VSS DQ36 DQ37 VDD DM4
Note 1. * : These pins are not used in this module. 2. Pins 71, 72, 73, 74, 77, 78, 79, 80, 83, 84 are reserved for x72 module, and are not used on x64 module. Pin 95,122 are NC for 8Mx16 based module & used for 16Mx8 based module. 3. Pins 89, 91 are reserved for x72 modules.
Pin Description
Pin Name A0 ~ A12 BA0 ~ BA1 DQ0 ~ DQ63 DQS0 ~ DQS7 CK0,CK0 ~ CK1, CK1 CKE0 ~ CKE1 CS0 ~ CS1 RAS CAS WE Function Address input (Multiplexed) Bank Select Address Data input/output Data Strobe input/output Clock input Clock enable input Chip select input Row address strobe Column address strobe Write enable Pin Name DM0 ~ 7 VDD VDDQ VSS VREF VDDSPD SDA SCL SA0 ~ 2 NC Function Data - in mask Power supply (2.5V) Power Supply for DQS(2.5V) Ground Power supply for reference Serial EEPROM Power Serial data I/O Serial clock Address in EEPROM No connection
Rev. 1.3 March. 2004
512MB Unbuffered SODIMM(based on sTSOP)
DDR SDRAM
FUNCTIONAL BLOCK DIAGRAM
CS1 CS0 DQS0 DM0
DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DM I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2 CS DQS
DQS4 DM4
DM I/O 0 I/O 1 I/O 6 I/O 7 I/O 2 I/O 3 I/O 4 I/O 5 CS DQS DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DM I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2 CS DQS
D0
D8
D4
DM I/O 0 I/O 1 I/O 6 I/O 7 I/O 2 I/O 3 I/O 4 I/O 5
CS
DQS
D12
DQS1 DM1
DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DM I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2 CS DQS
DQS5 DM5
D1
DM I/O 0 I/O 1 I/O 6 I/O 7 I/O 2 I/O 3 I/O 4 I/O 5 CS DQS
D9
DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47
DM I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2
CS
DQS
D5
DM I/O 0 I/O 1 I/O 6 I/O 7 I/O 2 I/O 3 I/O 4 I/O 5
CS DQS
D13
DQS2 DM2
DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DM I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2 CS DQS DM I/O 0 I/O 1 I/O 6 I/O 7 I/O 2 I/O 3 I/O 4 I/O 5 CS DQS
DQS6 DM6
DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DM I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2 CS DQS
D2
D10
D6
DM I/O 0 I/O 1 I/O 6 I/O 7 I/O 2 I/O 3 I/O 4 I/O 5
CS
DQS
D14
DQS3 DM3
DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DM I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2 CS DQS
DQS7 DM7
DM I/O 0 I/O 1 I/O 6 I/O 7 I/O 2 I/O 3 I/O 4 I/O 5 CS DQS DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 DM I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2 CS DQS
D3
D11
D7
DM I/O 0 I/O 1 I/O 6 I/O 7 I/O 2 I/O 3 I/O 4 I/O 5
CS DQS
D15
BA0 - BA1 A0 - A12 RAS CAS CKE1 CKE0 WE
BA0-BA1: DDR SDRAMs D0 - D15 A0-A12 : DDR SDRAMs D0 - D15 RAS CAS CKE CKE WE : DDR SDRAMs D0 - D15 : DDR SDRAMs D0 - D15 : DDR SDRAMs D8 - D15 : DDR SDRAMs D0 - D7 : DDR SDRAMs D0 - D15 CK0 / 1 Card Edge CK0 / 1 R=120 5%
D0,D8 / D4,D12 D1,D9 / D5,D13 D2,D10/ D6,D14 D3,D11/ D7,D15 *Clock Net Wiring
CK2 10pF CK2
VDDSPD VDD/VDDQ
SPD D0 - D15 D0 - D15 Notes : 1. DQ-to-I/O wiring is shown as recommended but may be changed. 2. DQ/DQS/DM/CKE/CS relationships must be maintained as shown 3. DQ, DQS, DM/DQS resistors: 22 Ohm.
VREF VSS
D0 - D15 D0 - D15
Rev. 1.3 March. 2004
512MB Unbuffered SODIMM(based on sTSOP)
Absolute Maximum Ratings
Parameter Voltage on any pin relative to VSS Voltage on VDD & VDDQ supply relative to VSS Storage temperature Power dissipation Short circuit current Symbol VIN, VOUT VDD, VDDQ TSTG PD IOS Value -0.5 ~ 3.6 -1.0 ~ 3.6 -55 ~ +150 1.5 * # of component 50
DDR SDRAM
Unit V V C W mA
Note : Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to recommend operation condition. Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
DC Operating Conditions
Parameter
Recommended operating conditions(Voltage referenced to VSS=0V, TA=0 to 70C)
Symbol
VDD VDDQ VREF VTT VIH(DC) VIL(DC) VIN(DC) VID(DC) VI(Ratio) II IOZ IOH IOL IOH IOL
Min
2.3 2.3 0.49*VDDQ VREF-0.04 VREF+0.15 -0.3 -0.3 0.36 0.71 -2 -5 -16.8 16.8 -9 9
Max
2.7 2.7 0.51*VDDQ VREF+0.04 VDDQ+0.3 VREF-0.15 VDDQ+0.3 VDDQ+0.6 1.4 2 5
Unit
V V V V V V V uA uA mA mA mA mA
Note
Supply voltage(for device with a nominal VDD of 2.5V) I/O Supply voltage I/O Reference voltage I/O Termination voltage(system) Input logic high voltage Input logic low voltage Input Voltage Level, CK and CK inputs Input Differential Voltage, CK and CK inputs V-I Matching: Pullup to Pulldown Current Ratio Input leakage current Output leakage current Output High Current(Normal strengh driver) ;VOUT = VTT + 0.84V Output High Current(Normal strengh driver) ;VOUT = VTT - 0.84V Output High Current(Half strengh driver) ;VOUT = VTT + 0.45V Output High Current(Half strengh driver) ;VOUT = VTT - 0.45V
1 2
3 4
Note : 1.VREF is expected to be equal to 0.5*VDDQ of the transmitting device, and to track variations in the dc level of same. Peak-to peak noise on VREF may not exceed +/-2% of the dc value. 2. VTT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set equal to VREF, and must track variations in the DC level of VREF 3. VID is the magnitude of the difference between the input level on CK and the input level on CK. 4. The ratio of the pullup current to the pulldown current is specified for the same temperature and voltage, over the entire temperature and voltage range, for device drain to source voltages from 0.25V to 1.0V. For a given output, it represents the maximum difference between pullup and pulldown drivers due to process variation. The full variation in the ratio of the maximum to minimum pullup and pulldown current will not exceed 1/7 for device drain to source voltages from 0.1 to 1.0.
Rev. 1.3 March. 2004
512MB Unbuffered SODIMM(based on sTSOP)
DDR SDRAM IDD spec table
M470L6423EN0 [ (32M x 8) * 8, 512MB Non ECC Module ]
Symbol IDD0 IDD1 IDD2P IDD2F IDD2Q IDD3P IDD3N IDD4R IDD4W IDD5 IDD6 Normal Low power IDD7A B3(DDR333@CL=2.5) 1,160 1,360 48 400 320 560 880 1,720 1,720 1,800 48 24 2,680 A2(DDR266@CL=2) 1,000 1,200 48 320 290 480 720 1,480 1,440 1,640 48 24 2,360 B0(DDR266@CL=2.5) 1,000 1,200 48 320 290 480 720 1,480 1,440 1,640 48 24 2,360
DDR SDRAM
(VDD=2.7V, T = 10C) Unit mA mA mA mA mA mA mA mA mA mA mA mA mA Optional Notes
* Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap.
Rev. 1.3 March. 2004
512MB Unbuffered SODIMM(based on sTSOP)
AC Operating Conditions
Parameter/Condition Input High (Logic 1) Voltage, DQ, DQS and DM signals Input Low (Logic 0) Voltage, DQ, DQS and DM signals. Input Differential Voltage, CK and CK inputs Input Crossing Point Voltage, CK and CK inputs Symbol VIH(AC) VIL(AC) VID(AC) VIX(AC) 0.7 0.5*VDDQ-0.2 Min VREF + 0.31 Max
DDR SDRAM
Unit V
Note 3 3 1 2
VREF - 0.31 VDDQ+0.6 0.5*VDDQ+0.2
V V V
Note : 1. VID is the magnitude of the difference between the input level on CK and the input on CK. 2. The value of VIX is expected to equal 0.5*VDDQ of the transmitting device and must track variations in the DC level of the same. 3. These parameters should be tested at the pim on actual components and may be checked at either the pin or the pad in simulation. the AC and DC input specificatims are refation to a Vref envelope that has been bandwidth limited 20MHz.
Vtt=0.5*VDDQ
RT=50 Output Z0=50 CLOAD=30pF VREF =0.5*VDDQ
Output Load Circuit (SSTL_2)
Input/Output Capacitance
Parameter Input capacitance(A0 ~ A11, BA0 ~ BA1,RAS,CAS,WE ) Input capacitance(CKE0, CKE1) Input capacitance(CS0, CS1) Input capacitance( CLK0, CLK1,CLK2) Input capacitance(DM0~DM7) Data & DQS input/output capacitance(DQ0~DQ63) Data input/output capacitance (CB0~CB7) Symbol CIN1 CIN2 CIN3 CIN4 CIN5 Cout1 Cout2
(VDD=2.5V, VDDQ=2.5V, TA= 25C, f=1MHz) M470L6423EN0 Min Max Unit
38 38 36 36 12 12 12
47 47 44 40 14 14 14
pF pF pF pF pF pF pF
Rev. 1.3 March. 2004
512MB Unbuffered SODIMM(based on sTSOP)
AC Timming Parameters & Specifications
Parameter
Row cycle time Refresh row cycle time Row active time RAS to CAS delay Row precharge time Row active to Row active delay Write recovery time Last data in to Read command Col. address to Col. address delay Clock cycle time Clock high level width Clock low level width DQS-out access time from CK/CK Output data access time from CK/CK Data strobe edge to ouput data edge Read Preamble Read Postamble CK to valid DQS-in DQS-in setup time DQS-in hold time DQS falling edge to CK rising-setup time DQS falling edge from CK rising-hold time DQS-in high level width DQS-in low level width DQS-in cycle time Address and Control Input setup time(fast) Address and Control Input hold time(fast) Address and Control Input setup time(slow) Address and Control Input hold time(slow) Data-out high impedence time from CK/CK Data-out low impedence time from CK/CK Input Slew Rate(for input only pins) Input Slew Rate(for I/O pins) Output Slew Rate(x4,x8) Output Slew Rate Matching Ratio(rise to fall) CL=2.0 CL=2.5
DDR SDRAM
Symbol
tRC tRFC tRAS tRCD tRP tRRD tWR tWTR tCCD tCK tCH tCL tDQSCK tAC tDQSQ tRPRE tRPST tDQSS tWPRES tWPRE tDSS tDSH tDQSH tDQSL tDSC tIS tIH tIS tIH tHZ tLZ tSL(I) tSL(IO) tSL(O) tSLMR
B3 (DDR333@CL=2.5)) Min
60 72 42 18 18 12 15 1 1 7.5 6 0.45 0.45 -0.6 -0.7 0.9 0.4 0.75 0 0.25 0.2 0.2 0.35 0.35 0.9 0.75 0.75 0.8 0.8 -0.7 -0.7 0.5 0.5 1.0 0.67 4.5 1.5 +0.7 +0.7 1.1 12 12 0.55 0.55 +0.6 +0.7 0.45 1.1 0.6 1.25 70K
A2 (DDR266@CL=2.0) Min
65 75 45 20 20 15 15 1 1 7.5 7.5 0.45 0.45 -0.75 -0.75 0.9 0.4 0.75 0 0.25 0.2 0.2 0.35 0.35 0.9 0.9 0.9 1.0 1.0 -0.75 -0.75 0.5 0.5 1.0 0.67 4.5 1.5 +0.75 +0.75 1.1 12 12 0.55 0.55 +0.75 +0.75 0.5 1.1 0.6 1.25 120K
B0 (DDR266@CL=2.5)) Min
65 75 45 20 20 15 15 1 1 10 7.5 0.45 0.45 -0.75 -0.75 0.9 0.4 0.75 0 0.25 0.2 0.2 0.35 0.35 0.9 0.9 0.9 1.0 1.0 -0.75 -0.75 0.5 0.5 1.0 0.67 4.5 1.5 +0.75 +0.75 1.1 12 12 0.55 0.55 +0.75 +0.75 0.5 1.1 0.6 1.25 120K
Unit
ns ns ns ns ns ns ns tCK tCK ns ns tCK tCK ns ns ns tCK tCK tCK ns tCK tCK tCK tCK tCK tCK ns ns ns ns ns ns V/ns V/ns V/ns
Note
Max
Max
Max
12
3
i,5.7~9 i,5.7~9 i, 6~9 i, 6~9 1 1
Rev. 1.3 March. 2004
512MB Unbuffered SODIMM(based on sTSOP)
B3 Min
12 0.45 0.45 2.2 1.75 6 75 200 7.8 tHP -tQHS tCLmin or tCHmin 0.55 0.4 18 (tWR/tCK) + (tRP/tCK) 0.6 0.4 20 (tWR/tCK) + (tRP/tCK) tHP -tQHS tCLmin or tCHmin
DDR SDRAM
B0 Max Min
15 0.5 0.5 2.2 1.75 7.5 75 200 7.8 0.75 0.6 0.4 20 (tWR/tCK) + (tRP/tCK) tHP -tQHS tCLmin or tCHmin 7.8 0.75 0.6
Parameter
Mode register set cycle time DQ & DM setup time to DQS DQ & DM hold time to DQS Control & Address input pulse width DQ & DM input pulse width Power down exit time Exit self refresh to non-Read command Exit self refresh to read command Refresh interval time Output DQS valid window Clock half period Data hold skew factor DQS write postamble time Active to Read with Auto precharge command Autoprecharge write recovery + Precharge time
Symbol
tMRD tDS tDH tIPW tDIPW tPDEX tXSNR tXSRD tREFI tQH tHP tQHS tWPST tRAP
A2 Max Min
15 0.5 0.5 2.2 1.75 7.5 75 200
Max
Unit
ns ns ns ns ns ns ns tCK us ns ns ns tCK
Note
7,8,9 7,8,9
4
1 5
3
tDAL
tCK
11
1. Maximum burst refresh cycle : 8 2. The specific requirement is that DQS be valid(High or Low) on or before this CK edge. The case shown(DQS going from High_Z to logic Low) applies when no writes were previously in progress on the bus. If a previous write was in progress, DQS could be High at this time, depending on tDQSS. 3. The maximum limit for this parameter is not a device limit. The device will operate with a great value for this parameter, but system performance (bus turnaround) will degrade accordingly. 4. A write command can be applied with tRCD satisfied after this command. 5. For registered DIMMs, tCL and tCH are 45% of the period including both the half period jitter (tJIT(HP)) of the PLL and the half period jitter due to crosstalk (tJIT(crosstalk)) on the DIMM. 6. Input Setup/Hold Slew Rate Derating Input Setup/Hold Slew Rate (V/ns) 0.5 0.4 0.3 tIS (ps) 0 +50 +100 tIH (ps) 0 +50 +100
This derating table is used to increase tIS/tIH in the case where the input slew rate is below 0.5V/ns. Input setup/hold slew rate based on the lesser of AC-AC slew rate and DC-DC slew rate. 7. I/O Setup/Hold Slew Rate Derating I/O Setup/Hold Slew Rate (V/ns) 0.5 0.4 0.3 tDS (ps) 0 +75 +150 tDH (ps) 0 +75 +150
This derating table is used to increase tDS/tDH in the case where the I/O slew rate is below 0.5V/ns. I/O setup/hold slew rate based on the lesser of AC-AC slew rate and DC-DC slew rate.
Rev. 1.3 March. 2004
512MB Unbuffered SODIMM(based on sTSOP)
8. I/O Setup/Hold Plateau Derating I/O Input Level (mV) 280 tDS (ps) +50 tDH (ps) +50
DDR SDRAM
This derating table is used to increase tDS/tDH in the case where the input level is flat below VREF 310mV for a duration of up to 2ns. 9. I/O Delta Rise/Fall Rate(1/slew-rate) Derating Delta Rise/Fall Rate (ns/V) 0 0.25 0.5 tDS (ps) 0 +50 +100 tDH (ps) 0 +50 +100
This derating table is used to increase tDS/tDH in the case where the DQ and DQS slew rates differ. The Delta Rise/Fall Rate is calated as 1/SlewRate1-1/SlewRate2. For example, if slew rate 1 = 5V/ns and slew rate 2 =.4V/ns then the Delta Rise/Fall Rate =-0/5ns/V. Input S/H slew rate based on larger of AC-AC delta rise/fall rate and DC-DC delta rise/fall rate. 10. This parameter is fir system simulation purpose. It is guranteed by design. 11. For each of the terms, if not already an integer, round to the next highest integer. tCK is actual to the system clock cycle time.

The following table specifies derating values for the specifications listed if the single-ended clock skew rate is less than 1.0V/ns. CK slew rate (Single ended) 1.0V/ns 0.75V/ns 0.5V/ns tIH/tIS (ps) 0 +50 +100 tDSS/tDSH (ps) 0 +50 +100 tAC/tDQSCK (ps) 0 +50 +100 tLZ(min) (ps) 0 -50 -100 tHZ(max) (ps) 0 +50 +100
Rev. 1.3 March. 2004
512MB Unbuffered SODIMM(based on sTSOP)
Command Truth Table
COMMAND Register Register Extended MRS Mode Register Set Auto Refresh Refresh Entry Self Refresh Exit
CKEn-1
DDR SDRAM
(V=Valid, X=Dont Care, H=Logic High, L=Logic Low)
CKEn CS RAS CAS WE BA0,1 A10/AP A12, A11 A9 ~ A0 Note
H H H
X X H L H X X
L L L L H L L
L L L H X L H
L L L H X H L
L L H H X H H V V
OP CODE OP CODE X
1, 2 1, 2 3 3 3 3
L H H
X Row Address L H L H X V X L H X
Column Address Column Address
Bank Active & Row Addr. Read & Column Address Write & Column Address Burst Stop Precharge Bank Selection All Banks Entry Exit Entry Precharge Power Down Mode Exit DM No operation (NOP) : Not defined Auto Precharge Disable Auto Precharge Enable Auto Precharge Disable Auto Precharge Enable
4 4 4 4, 6 7
H H H
X X X
L L L H L X H L H L
H H L X V X X H X V X
L H H X V X X H X V
L L L X V X X H X V
V
5
Active Power Down
H L H
L H L
X
X
L H H
H
X X H X H X
8 9 9
X
H L
X H
Note : 1. OP Code : Operand Code. A0 ~ A12 & BA0 ~ BA1 : Program keys. (@EMRS/MRS) 2. EMRS/ MRS can be issued only at all banks precharge state. A new command can be issued 2 clock cycles after EMRS or MRS. 3. Auto refresh functions are same as the CBR refresh of DRAM. The automatical precharge without row precharge command is meant by "Auto". Auto/self refresh can be issued only at all banks precharge state. 4. BA0 ~ BA1 : Bank select addresses. If both BA0 and BA1 are "Low" at read, write, row active and precharge, bank A is selected. If BA0 is "High" and BA1 is "Low" at read, write, row active and precharge, bank B is selected. If BA0 is "Low" and BA1 is "High" at read, write, row active and precharge, bank C is selected. If both BA0 and BA1 are "High" at read, write, row active and precharge, bank D is selected. 5. If A10/AP is "High" at row precharge, BA0 and BA1 are ignored and all banks are selected. 6. During burst write with auto precharge, new read/write command can not be issued. Another bank read/write command can be issued after the end of burst. New row active of the associated bank can be issued at tRP after the end of burst. 7. Burst stop command is valid at every burst length. 8. DM sampled at the rising and falling edges of the DQS and Data-in are masked at the both edges (Write DM latency is 0). 9. This combination is not defined for any function, which means "No Operation(NOP)" in DDR SDRAM.
Rev. 1.3 March. 2004
512MB Unbuffered SODIMM(based on sTSOP)
PACKAGE DIMENSIONS
DDR SDRAM
Units : Inches (Millimeters)
2.70 (67.60) 2.50 (63.60) 0.16 0.039 (4.00 0.10) 0.79 (20.00) 0.24 (6.0)
Full R 2x 1.25 (31.75) (2.55 Min)
1 0.456 11.40
3941 1.896 (47.40)
199
0.086 2.15
0.07 (1.8) 0.098 2.45 2 4042
0.17 (4.20) 0.096 (2.40) Z
2- 0.07 (1.80)
Y 200
0.150 Max (3.80 Max) (4.00 Min) (4.00 Min) 0.157 Min 0.157 Min 0.16 0.0039 (4.00 0.10) 0.04 0.0039 (1.00 0.1)
0.102 Min
0.018 0.001 (0.45 0.03)
0.008 3/4 0.006 (0.20 3/4 0.15 ) 0.024 TYP (0.60 TYP)
0.04 0.0039 (1.00 0.10)
Detail Z
Detail Y
Tolerances : .006(.15) unless otherwise specified The used device is 32Mx8 DDR SDRAM, sTSOP-300mil SDRAM Part No. : K4H560838E-N***
Rev. 1.3 March. 2004

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